1. Field of the Invention
The present invention relates to a dielectric capacitor which is useful as a capacitor for large scale integrated circuit (LSI), particularly as a capacitor for memory, as well as to a process for producing the dielectric capacitor.
2. Description of the Related Art
Currently, researches and developments, or proposals are being made on ferroelectric non-volatile memories obtained by integration of a capacitor using, as its capacitive insulating layer, a ferroelectric such as PZT (PbZr.sub.x Ti.sub.1-x O.sub.3), SrBi.sub.2 Ta.sub.2 O.sub.9 or the like. An example thereof is a memory cell comprising one transistor and one capacitor, described in Japanese Patent Application Laid-Open No. 275792/1994. This memory cell is explained with reference to FIG. 7. In the memory cell, on a silicon substrate 701 are formed (1) a MOS (metal oxide semiconductor) transistor comprising source and drain gates and (2) a capacitor (isolated and insulated from the transistor by an insulating layer 712), comprising an upper electrode 708, a lower electrode 706 and a ferroelectric 707 interposed between the two electrodes; in the insulating layer 712 isolating the above two elements (1) and (2) are formed contact holes 710a, 710b, 710c and 710d communicating with a source region, a drain region, the lower electrode and the upper electrode; a metal is filled in at least one layer in these contact holes; and wiring metal layers 711a, 711b and 711c are contacted with the metal filled in the contact holes.
In FIG. 7, 702a and 702b refer to source and drain regions; 703 refers to a field oxide layer; 704 refers to a gate oxide layer; 705 refers to a gate electrode; and 709a and 709b each refer to a barrier metal layer. 711a and 711b each refer to an metal wiring.
Also in Japanese Patent Application Laid-Open No. 110110/1993 is disclosed a structure as shown in FIG. 8, in which a ferroelectric 807 constituting a capacitor is disposed in a grove formed in the portion of a silicon substrate where the source and drain layer 804 (a diffused layer containing a high concentration of a dopant) of a transistor is disposed.
In FIG. 8, 801 refers to a P type silicon substrate; 802 refers to a LOCOS isolating layer; 803 and 804 are a source and a drain; 805 refers to a gate electrode; 806 refers to an insulating layer for layer insulation; 808 refers to an upper electrode; 809 refers to an insulating layer for layer insulation; and 810a and 810b are each an aluminum wiring.
Also in Japanese Patent Application No. 161854/1995 is disclosed a memory cell in which a capacitor is disposed in the back channel of a thin-layer transistor and the polarization property of the capacitor is reversed by a weak current. This memory cell is formed as shown in FIG. 9. That is, a polycrystalline silicon layer 903 is formed on a field oxide layer 902 formed on a silicon substrate 901; thereon is formed a silicon oxide layer 904; then, a groove is formed in the silicon oxide layer 904; in the groove is filled a ferroelectric (e.g. PZT) 905; on the ferroelectric 905 is formed, via a silicon oxide layer 906, a thin-layer transistor having diffused layers as source and drain regions. The silicon oxide layer 906 formed between the ferroelectric and the active layer of the thin-layer transistor is for controlling the level difference appearing at the interface between the ferroelectric (particularly PZT layer) and the silicon layer.
In FIG. 9, 907a and 907c refer to a source and a drain; 907b refers to a channel region; 908 refers to a gate oxide layer; 909 refers to a gate polysilicon; 910 refers to a contact hole; and 911 refers to a bit line.
In production of a capacitor used in conventional LSI's such as above-mentioned memory cells, there have been the following problems.
The first problem is the quality deterioration of ferroelectric occurring during the formation of insulating layer for layer insulation. For example, in the ferroelectric memory cell described in Japanese Patent Application Laid-Open No. 275792/1994, the ferroelectric of capacitor formed on the lower electrode is exposed, during the formation of a silicon oxide layer 712 (an insulating layer for layer insulation), to an atmosphere for formation of the layer 712. This atmosphere is a reducing atmosphere containing a high concentration of hydrogen, when the silicon oxide layer 712 is formed from silane by CVD; therefore, when the ferroelectric is made of an oxide, the surface thereof is reduced and deteriorated.
The second problem occurs when the silicon oxide layer formed contains a large amount of water. When a boron or phosphorus-containing silicon oxide layer [e.g. BPSG (borophosphosilicate glass) layer, BSG (borosilicate glass) layer or PSG (phosphosilicate glass) layer] or an ozone-TEOS (tetraethoxysilane) layer (this layer is formed at low temperatures) is formed so as to cover the capacitor, the silicon oxide layer contains a large amount of water in some cases, which may deteriorate the leak current property and insulation property of capacitor.
The third problem is appearance of difference in levels and an increase in number of steps. For example, when a ferroelectric element is formed on a field oxide layer 703 as shown in FIG. 7 (Japanese Patent Application Laid-Open No. 275792/1994), the difference in levels appearing in an outermost layer 712 is very large owing to the formation of a lower electrode 706, a dielectric layer 707, etc., making difficult one-shot focussing in light exposure for holes making. Hence, focussing and light exposure must be made to each different level to form individual contact holes, inviting an increase in number of steps. When, in this constitution, the insulating layer for layer insulation is formed so as to have a flat surface based on the thickness of the part of the insulating layer on the capacitor, the thickness of the insulating layer is too large depending upon its position, which may make too large the depths of some contact holes and may make difficult the implantation of wiring metal in these holes.
As the fourth problem, there can be mentioned the problems occurring when a ferroelectric and silicon are in direct contact, as seen in the structures of FIG. 8 (Japanese Patent Application Laid-Open No. 110110/1993) and FIG. 9 (Japanese Patent Application Laid-Open No. 161854/1995); that is, a problem that a ferroelectric metal and silicon react with each other easily during the heating step for formation of ferroelectric layer and a problem that, during the heating step, silicon is easily oxidized and thereby a silicon oxide layer is easily formed between the ferroelectric and the silicon layer. In general, a ferroelectric has a dielectric constant considerably larger than that of a silicon oxide layer. Therefore, when a silicon oxide layer is formed between the ferroelectric layer and the silicon layer, there is formed a structure in which a dielectric of larger dielectric constant and a dielectric of small dielectric constant are interposed in series between two electrodes; when a voltage is applied to this structure, the voltage is distributed so that a higher voltage is applied to the dielectric of small dielectric constant. In other words, a voltage is applied to the silicon oxide layer formed between the ferroelectric and silicon and, as a result, the ferroelectric is unable to show a desired polarization property.
The fifth problem is the formation of short circuit between upper and lower electrodes, which may occur in producing a capacitor comprising an upper electrode, a lower electrode and a ferroelectric interposed between the two electrodes, according to a conventional process by using, as a metal for electrode, a sparingly reactive metal (e.g. Pt or Au). The process for producing a capacitor is largely classified into the following three processes from the reasons of circuit designing. The first process is a process which comprises forming a lower electrode layer, a ferroelectric layer and an upper electrode layer successively in this order and then etching, using a mask, these three layers in the order of the upper electrode layer to the lower electrode layer so as to give a desired shape. The second process is a two-step process which comprises forming a lower electrode layer, processing the layer into a desired shape, then forming thereon a ferroelectric layer and an upper electrode layer in this order, and processing the two layers into a desired shape. The third process is a two-step process which comprises forming a lower electrode layer and a ferroelectric layer, processing them into a desired shape, then forming an upper electrode layer, and processing the layer into a desired shape. In the first and second processes, the lower electrode is subjected to plasma etching after the ferroelectric layer beneath the upper electrode has been etched. At this time, when the lower electrode is made of a sparingly reactive metal, the metal surface is hit by the accelerated ion in plasma; the sputtered metal atoms adhere to the side of the already shaped ferroelectric layer; thereby, a side wall layer may be formed. When the side wall layer made of a sparingly reactive metal grows to such an extent as the layer connects the upper and lower electrodes, a short circuit is formed and no desired capacity property is obtained. In the third process as well, there may occur the short-circuiting between the upper and lower electrodes owing to the wrong positioning during light exposure. That is, when an upper electrode layer is formed on a shaped lower electrode and a shaped ferroelectric layer and the resulting material is subjected to light exposure and etching, the size of a mask for light exposure is made smaller than the sizes of the shaped lower electrode and the shaped ferroelectric layer so that the contact area between the lower electrode and the upper electrode layer can be etched. At this time, if wrong positioning is made in light exposure, some part of the contact area between the lower electrode and the upper electrode layer is covered by an etching resist and remains unetched, which invites short-circuiting. Precise positioning can be achieved by making large the difference between the size of upper electrode and the sizes of ferroelectric and lower electrode. However, the size of capacitor is inevitably small in order to achieve high integration, which in turn makes it impossible to secure the area sufficient for the above large difference between the size of upper electrode and the sizes of ferroelectric and lower electrode.